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AI cuts chip design to 3 months; silicon still takes 9

Pat Gelsinger, ex-Intel and VMware CEO, on why 100 AI chip startups will consolidate, why memory and optics are next, and why power limits AI.

Pat GelsingerNvidiaIntelVMwared-MatrixSemiconductorsMemoryEnergyAI Infrastructure
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AI cuts chip design to 3 months; silicon still takes 9

Recorded 09 October 2026 · 53 min

Pat Gelsinger, who led Intel and VMware and is now a general partner at Playground Global, talks with two former colleagues about what AI changes in chip design and what it leaves untouched. His central point is that AI has made design the easy part. A strong chip can be designed in 3 months, but it takes 9 months to turn that into usable silicon, packaging and a rack. The bottleneck has moved to fabrication, memory, power delivery and the grid itself.

The tension is speed against physics. AI compresses logic and software work, while lithography, yields, thermals and grid capacity run on clocks measured in years. That shapes his calls: roughly 100 AI chip startups will consolidate, memory is due its first real innovation in 30 years, optics will replace copper for scale-up around 2028-29, and energy will cap how far AI spending runs. One interviewer, Guido, pushes back that agents make chip diversity cheap.

  1. Logic yields, analog doesn't — ▶ 7:32

    Chip design is at a turning point like the 486 was for EDA. Many logic functions can now be done with AI tools "in pretty incredible ways" because transistor budgets are big and a few experts can guide the tools. Analog is not AI-able yet: it needs lots of silicon data, so designers either get very conservative or do it the hard way. His rule: whenever technology makes something easy, the bottleneck moves somewhere else.

  2. 3 months to design, 9 to use — ▶ 9:21

    Design now takes 3 months, but fab needs at least 3 months even with supercharged flows. Advanced 3D packaging adds roughly 3 more, then it has to become a rack, because "nothing's a chip anymore. It's a rack." At 18 months to scale with software, workload understanding is stale; Graphcore was not a bad design, but the world moved on. His target is a month or two, which needs new lithography and flows without $50 million of mask cost before prototyping.

  3. HBM and the 40% power tax — ▶ 11:54

    HBM is "a hideous memory" and simply the best available: poor bit density, bandwidth capped by shoreline, power and thermal problems, and DRAM dislikes heat. AI is a memory-compute workload, so this is a critical bottleneck. Power is the other. There are no good 3D tools for power dissipation and hotspots, so designers guard-band nearly the whole power envelope and lose about 40% of their power. Power modeling, dissipation and the delivery model all have to improve.

  4. 100 chips will converge — ▶ 14:38

    He expects the field to narrow for three reasons. Workloads keep migrating (prefill, midfill, decode, CPU-like reasoning, 64-bit precision returning for chemistry), so extreme specialization will not fit workloads 2-4 years out. Scale requires capital and workloads, and 100 vendors cannot all get them. And big buyers will pick winners: OpenAI, Nvidia and Anthropic will favor hardware whose software co-evolves with their models. He thinks LLMs are also nearing their limits, which will shift algorithms again.

  5. Agents versus capital — ▶ 19:12

    Guido argues that software complexity once limited the industry to a few architectures, but an agent swarm can now write an optimized kernel overnight, so more heterogeneity is plausible. Gelsinger's reply is time and money: 18 months to build, then "could I borrow 50 billion" for racks, data centers and power at scale. Nvidia's Groq deal shows his expected path: in 2 years you won't tell what Groq is inside Nvidia. The heterogeneity gets hidden by abstraction, not removed.

  6. Zero new memories in 30 years — ▶ 22:50

    He has been associated with at least 5 new memory architectures, Optane among them, and knows of about 100 proposed over 30 years. Major new ones: zero. Beyond DRAM, SRAM and flash, nothing. Memory made money about one year in five, but all three big vendors are now in the top 20 most valuable companies, with roughly $2.5 trillion of added market cap in 4 years. He expects ferroelectrics and stackable, non-capacitive dense cells to follow, and says he has a stealth memory company. He is cool on flash and MRAM.

  7. Mid-rise stacks, not skyscrapers — ▶ 27:40

    Stack value rises with height, so per-layer yield must improve exponentially. Spare lines help, but a cracked die is a bad die. He is "not a crazy 16 32 stack kind of guy": 2-4 high memory stacks are the sweet spot. Even then, once power delivery in the Z dimension, redistribution layers and optics are added, a canonical package is already about 8 layers thick. He calls it an engineering feat and a manufacturing nightmare, and says engineers are becoming plumbers, with liquid cooling and diamond as options.

  8. No to optical memory, no to PIM — ▶ 32:13

    Moving memory off-package over optics means more optical-electrical conversions and more power burned. Compute costs few femtojoules per operation, while communication per bit is comparatively 1,000x worse. Processing-in-memory fails differently: it forces workloads to push compute into memory. PIM ideas have been around 25-30 years and he expects them still hanging around in 25-30 more. He allows he could be wrong, but wants high-density, high-bandwidth memory close to compute as the more generalizable answer.

  9. Optics for scale-up, 2028-29 — ▶ 34:54

    Copper is a shrinking waveguide: making it work at 5 m now costs more than making optical work at 100 m. The holdup is an optical supply chain never tested at scale, with laser capacity, thermals and packaging unresolved. He expects co-packaged and near-packaged optics around 2028-29 for 10 million GPU scale. He calls the NVL72 an engineering marvel and a manufacturing nightmare that cost the industry an extra 1.5 years. Large, predictable AI flows suit optical circuit switching, which dissolves the scale-up and scale-out boundary.

  10. Energy caps the euphoria — ▶ 43:22

    The US spent 10-15 years flat, retiring coal as fast as it added renewables, and now grows capacity perhaps 4% a year. Gas turbine lead times are 8 years, renewables depend on China, and the last US reactor came online 20 years ago. He expects more data center projects to default because the energy won't be there, an upper bound on AI spending. Inside the building he points to 800V DC, vertical GaN converting 800V to 5V in one step, and a superconducting company, Snowcap, claiming 1,000x better power performance.

  11. VMware for agents — ▶ 48:44

    Every innovation leads to the next abstraction, and the virtual machine deserves a permanent place in the compute hierarchy. Agent swarms raise questions VMware once answered for hardware: who manages the agents, sets their security profiles and watches their performance? He wants every element of virtualization and management rebuilt, with vMotion-style migration for agents. Humans need to set policies, write "constitutions" and watch dashboards. The design constraint changes from abstracting hardware for applications to abstracting hardware and operations for agents.

The open question. Gelsinger's case for consolidation leans on workloads shifting too fast for specialized chips. Yet his own examples of that shift (early prefill, midfill, decode, CPU-like reasoning, 64-bit chemistry) are arguments for more specialization, which he resolves by saying Nvidia will absorb it, as with Groq. That is consolidation by acquisition, not proof that 100 designs cannot each find a niche. Watch whether OpenAI and Anthropic actually back a handful of accelerators, and whether the heterogeneity stays visible or gets hidden inside a few vendors.

Watch the full video at https://www.youtube.com/watch?v=1Q_7yU7FZ1k.

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