Intel says leading-edge chip output can only double, not 10x

1. Node bring-up is defect hunting — ▶ 1:22

   14A has been in development for 3+ years and is close to finalizing its process and tool sets. The factory runs about 2,000 steps, and each must be tuned so the node can run thousands of wafers a week, repeatably. Defects surface two ways: inline metrology during the flow, and end-of-line electrical test or sort. Failures get cross-sectioned in the TEM lab. The layer a defect sits between points to the section of the flow responsible, and the inline metrology there shows which defects to chase.

2. 10nm taught restraint — ▶ 2:57

   10nm was targeted for 2016 and began manufacturing in 2018. Intel pursued "hyperscaling", scaling faster than historical rates, and engineered around tools that weren't ready, which loaded the process and the engineers. EUV is the item Auth names. Intel judged it unready, while TSMC put it into volume in 2019, and Intel's first EUV process reached products in 2023. The 10nm process ended with world-class yield, performance and cost, but late. The fixes are less innovation per node and phase gates with yield, defect and performance criteria. Anything that misses moves to the next node.

3. Don't tackle it before you must — ▶ 9:58

   Gate-all-around was known in the '90s and demonstrated in 1988, a year before FinFET, yet FinFET reached Intel volume production in 2011 and Samsung's first gate-all-around chips came in 2022. Auth's rule is that you don't tackle something before you have to. Strained silicon, high-K metal gate and FinFET came first. Gate-all-around then needed new materials plus vendor inventions like new deposition gases and a heating chuck. Since the 2000s, process work has shifted from "try to not change anything" to tearing things up, with roughly 10x more materials than in the '90s.

4. Same tool, opposite conclusions — ▶ 14:45

   High-NA widens numerical aperture from 0.33 to 0.55, printing features about 1.7x smaller in one pass. The machines cost roughly twice the $200 million of standard EUV. Intel's backside power moves power lines under the transistors, relaxing front-side pitch enough that one High-NA pass suffices. TSMC lacks backside power, needs tighter pitches, and still has to double-pattern EUV, so High-NA doesn't help it. At 14A, Intel leaves High-NA as an option in the PDK, decided customer by customer because it adds complexity.

5. Thermals cap 3D, visibility is four years — ▶ 21:16

   Compute is limited by three things: switching frequency, power per switch, and heat dissipation. Logic burns more power than memory, so it can't be stacked like HBM or 3D NAND. Auth says system-level thermal simulation tools are "in its infancy". The limit is real but solvable. Copper stays for larger lines and gets replaced at the tightest pitches. Intel sees about four years of scaling visibility at a time. Over 20 years, he expects exotic structures, and he expects DRAM to go 3D as NAND already has.

6. Ship before the data is complete — ▶ 25:06

   Kevin Fischer runs the Hot Topics meetings on 18A and 18A-P. His rule is that you never get a complete data set, and waiting for one is already too late. The job is deciding how much production risk to take. The example is epi nodules, tumor-like abnormal growth in source and drain epitaxy that shorts transistors. Teams chase every fix in parallel, including a special clean and removing the source. Priority lots use HotBox 1, which gets priority at every tool. It is a carpool lane that drags on the whole factory.

7. Ruthenium and CFET live in short loops — ▶ 30:01

   Ruthenium can be etched and needs no resistive liner. It overtakes copper at roughly 20nm pitch. Intel picked cobalt at 10nm, then copper came back as vendor solutions improved, and ruthenium may follow. CFET stacks n-type and p-type devices, but vertical connections raise etch and fill aspect ratios, and fills can leave air gaps. Intel qualifies unit cells in short-loop vehicles instead of waiting a month for a full flow, starting with one ribbon on one. Ideas die on basics like adhesion or non-hermetic caps.

8. Hybrid bonding rewrites the pitch — ▶ 43:53

   Compute grows with area while chip-to-chip links grow with perimeter, so data movement lags. Wafer-to-wafer bonding needs matching dies, and random good/bad pairing wastes yield. Chip-to-wafer bonds only known-good dies, and Intel will do both, with chip-to-wafer favored for logic-on-logic. First-level interconnect pitch went from 130-150 micrometers 15 years ago to 25 in Foveros production, with sub-10 in the lab. A paper this year showed reliable 0.45 micron pitch. That approaches back-end wire pitch and could remove interconnect layers.

9. Tools cap output near 2x — ▶ 48:16

   ASML makes fewer than 100 EUV tools a year and won't plan significantly more by 2030, and every other tool category is also short. Processes lock to specific tools, so Intel aims for about 80% tool reuse from 18A to 14A. Asked about 10x wafers, Ranade says "Not 10X, but probably 2X." Tools ordered now take 18 months, which lands in 2028, and new fab shells push capacity to the decade's end. He accepts the summary that next year's output could exceed forecasts but 2030's won't. Model companies could consume whole fabs, making the industry "virtually vertically integrated".

10. Scale economics and the catch-up claim — ▶ 53:36

    About 80% of a fab's cost is fixed, so each point of utilization and yield matters, and moving from 60% to 70% die yield is not linear. Ranade says there are three advanced foundries left from about 20 forty years ago. TSMC ships over 3x Intel's wafers, which Ranade says Intel will close only gradually. On technology he claims parity, within a few percent, arguing on-time delivery and high yield matter more. TSMC's CapEx is about $50 billion against Intel's $20 billion. He concedes Intel would have invested more "a year ago" had it known.

11. Fab costs can't keep doubling — ▶ 1:03:03

    Fab cost doubles every 4-5 years, and lithography is rising faster. A High-NA scanner with its equipment costs about $400 million, and extrapolating gives $800 million in four years, which "doesn't really make sense". Ranade argues the industry is risk-averse for good reason, with tens of billions at stake, and that engineers take today's process flow as gospel. He asks whether clean rooms are even necessary, noting that no incumbent would run a hamburgers-and-cigars experiment. Chip design flows, he says, were also locked in 30 years ago.

Capital does not buy leading-edge silicon on a short clock. The binding constraint is equipment, and the equipment comes from a few vendors who are not scaling at AI's pace. ASML builds fewer than 100 EUV machines a year and does not plan significantly more by 2030. That supply is split between Intel, TSMC and the memory makers. EUV is not even the only shortage. Pushkar Ranade says every tool category is tight, and the problem compounds because a process locks you to a specific tool from a specific supplier. Once 18A is set, you cannot shop around.

Asked whether the world has enough tools to make 10x the wafers, Ranade answers "Not 10X, but probably 2X." AI has tripled compute every year for a decade, and he says that cannot continue unless every tier of the supply chain, down to the sub-suppliers, expands at once. The calendar makes it worse. Tools ordered today take 18 months, which puts delivery in 2028. A new fab shell pushes real capacity to the end of the decade. He accepts the summary that output next year could beat forecasts, but output in 2030 will not.

The obvious objection is that AI economics should fix this. Patel notes that a couple of billion dollars of Intel CapEx yields logic for something like $100 billion of annual model revenue, so labs should simply guarantee demand and fund everything. Ranade says early signs of that are visible. Some model companies could consume a whole fab or several, and hyperscalers already design their own chips. The industry is drifting from horizontal back toward what he calls "virtually vertically integrated". But money has limits. A new fab such as the Terafab with Elon Musk gives its owner guaranteed supply and does not add much silicon while tools are scarce. Power, water and clean-room space can be scaled in ways tools cannot, and that is the only relief he offers.

That leaves Intel's own position, and here Ranade makes his boldest claim. The gap to TSMC is scale, not technology. TSMC ships more than 3x the leading-edge wafers, and in a business where 80% of cost is fixed, scale is the purest economic force. Every point of utilization counts, and lifting die yield from 60% to 70% is a nonlinear gain. On technology he says Intel is "already there", a few percent off on power, performance or area. He rejects a benchmark that puts 14A near TSMC's N2 on density and argues the real test is being on time with yields high enough for rapid ramps.

That test is Intel's own scar tissue. The 10nm node was aimed at 2016 and began manufacturing in 2018. Intel scaled far faster than history and engineered around tools that were not ready, and the burden fell on the process and its engineers. Chris Auth calls 10nm a great technology that arrived late. EUV is the item he names. Intel judged it unready, TSMC put it into volume in 2019, and Intel's first EUV product arrived in 2023, giving TSMC about four more years of experience with the machines. The institutional fix is restraint. Do not put too much innovation into one node. Gate candidates on yield, defect and performance criteria, and let whatever misses move to the next node.

Restraint explains why technology that exists takes decades to ship. Gate-all-around was demonstrated in 1988, a year before FinFET. FinFET reached Intel production in 2011 and gate-all-around reached Samsung's in 2022. Auth's rule is that you do not tackle something before you have to. Strained silicon, high-K metal gate and FinFET each bought performance first. When gate-all-around finally became necessary, it needed new deposition gases and heating chucks, which only the tool vendors could invent. The dependence on suppliers that caps output also paces the research.

Inside a node, the work is brutal triage. A flow has about 2,000 steps, and defects are found by inline metrology and end-of-line test, then cross-sectioned to find the layer at fault. Kevin Fischer decides which problems get engineers and wafers. His principle is blunt: "If you want to wait for a complete data set, you've waited too long." The job is pricing risk, not removing it. Epi nodules, growths that short neighboring transistors, get parallel fixes. The most urgent lots ride HotBox 1, a lane that hurts the whole factory but moves one experiment fast.

The technical bets show the other route to the same constraint, which is getting more from each tool. Backside power relaxes front-side pitch, so Intel can print with a single High-NA pass. TSMC, without backside power, still needs double-patterned EUV and finds the tool unhelpful. Ruthenium beats copper below roughly 20nm pitch because it needs no liner. CFET stacks transistors but runs into etch and fill aspect ratios, and the stacked version in the lab may not yet beat side-by-side ribbons. Hybrid bonding is the largest lever. Pitches have gone from 130-150 micrometers to 25 in production, and a conference paper this year showed reliable bonding at 0.45 microns. Ranade says Intel will bond both wafer-to-wafer and chip-to-wafer, with chip-to-wafer favored where only known-good dies should be paired.

What stays unresolved is whether the cost curve can survive any of this. Fab cost doubles every 4-5 years, and a High-NA scanner with its equipment already costs about $400 million. Ranade calls the extrapolation senseless and wonders aloud whether clean rooms are even needed, noting that no incumbent would run a hamburgers-and-cigars experiment. Nobody with tens of billions at stake will volunteer. Asked whether Intel should lock up tools now, he says it would have invested more a year ago and will invest more now. How much more, and whether tool makers can build it in time, goes unanswered.